All Logic and Boolean	

	Name:	
________________________	

Class:	
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Date:	
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Time:	189 minutes	
Marks:	169 marks	
Comments:		

Q1.
A security system uses the control port shown below.

The purpose of each bit is shown in the diagram.
Bits 0 to 4 are inputs, bit 5 is not used and should always be zero, bits 6 and 7 are output bits.
The bit pattern shown occurs when the system is first activated.
Detection of movement results in the corresponding bit being set to 1.
Breaking of a contact results in the corresponding bit being set to 0.
Bits 6 and 7 will turn on the security light and alarm respectively when set to 1.
The system, if activated, must turn on the security light if external movement is detected. The alarm must be turned on if either or both contacts are broken or if internal movement is detected.
(a)     Give the masks and the logical operations needed for each of the following. In each case all other bits must remain unchanged.
(i)      Testing the state of the external movement sensor.
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(ii)     Turning on the alarm.
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(4)
(b)     Write an algorithm for the procedure required to check the sensors and contacts and to activate the alarm or security light when necessary.

 

 

 
(7)
(Total 11 marks)
Q2.
(a)     What is the name of the logic gate represented by the truth table and symbol shown in Figure 1?
Figure 1
 
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(1)
Figure 2 shows a logic circuit that might be found inside a processor.
Figure 2
 
(b)     The value at M (indicated by the arrow in Figure 2) is represented by the following Boolean expression.
 
Simplify this Boolean expression.
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(1)
(c)     The output T (in Figure 2) is represented by the following Boolean expression.
 
Simplify this Boolean expression.
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(1)
(d)     Complete the missing cells in the table.
Four rows of the truth table for the circuit in Figure 2
 
Inputs	Outputs	
C	B	A	T	S	R	
0	0	0	0	0	0	
0	0	1	 	 	 	
0	1	0	 	 	 	
0	1	1	0	1	0	
(3)
(e)     The logic circuit shown in Figure 2 obtains the two’s complement of a 3-bit binary number. Explain how this circuit could be used by a processor when subtracting one 3-bit binary number from another.
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(1)
(f)     The circuit in Figure 2 can be simplified so that it uses fewer logic gates but still has the same functionality. Changing the design of the circuits used in a processor can improve processor performance. Increasing the number of cores can also improve processor performance.
State three other factors that can improve processor performance. For each factor, explain how it will improve processor performance.
Factor: ____________________________________________________________
How improves: _____________________________________________________
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Factor: ____________________________________________________________
How improves: _____________________________________________________
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Factor: ____________________________________________________________
How improves: _____________________________________________________
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(6)
(Total 13 marks)
Q3.
(a)     (i)      State the name of the logic gate that is represented by the truth table below.
 
 	Inputs	Output	
 	A	B	Q	
 	0	0	0	
 	0	1	0	
 	1	0	0	
 	1	1	1	
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(1)
(ii)     State the name of the logic gate that is represented by the truth table below.
 
 	Inputs	Output	
 	A	B	Q	
 	0	0	1	
 	0	1	0	
 	1	0	0	
 	1	1	0	
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(1)
(b)     A fish tank has a controller that can monitor sensors and control external devices.
•        Sensor A returns a 1 (true) when the water level is too low and a 0 (false) otherwise
•        Sensor B returns a 1 (true) when the water level is too high and a 0 (false) otherwise
•        Sensor C returns a 1 (true) when the water temperature is above 28°C and a 0 (false) otherwise
•        Sensor D returns a 1 (true) when the water temperature is below 23°C and a 0 (false) otherwise.
The controller also has outputs to the following devices:
•        The heater is turned on when output H is 1 (true) and turned off when output H is 0 (false)
•        The top-up water pump is on when output J is 1 (true) and turned off when output J is 0 (false)
The controller can also read the current state of both H and J to see whether the devices are turned on or off.
(i)      The top-up water pump is turned on and off according to the Boolean equation:
 
Draw the logic circuit corresponding to this equation in the box below.
 
(2)
(ii)     A fault alarm should sound when either of the following two conditions are met:
•        if the water temperature is above 28°C and the heater is on
•        if the water level is too low and the top-up water pump is not on.
Write a Boolean equation to represent the logic required to turn the fault alarm on when either or both of these conditions are met.
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(3)
(c)     Without using a truth table, simplify the following Boolean expression:
 
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(3)
(Total 10 marks)
Q4.
(a)     Complete the table below and draw the symbol for an AND gate in the box.
 
Truth table for an AND gate	 	AND gate symbol	
Input A	Input B	Output			

 	 	 			
 	 	 			
(2)
(b)     Using the laws of Boolean algebra, simplify the following Boolean expression.
A.B. (A + B)
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(3)
(c)     Using the laws of Boolean algebra, simplify the following Boolean expression.
(X + Y).(X + )
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Answer ___________________________
(3)
(Total 8 marks)
Q5.
A burglar alarm system is to be implemented that has the following sensors:
•        a door sensor D that outputs TRUE when the door is open and FALSE when the door is shut
•        a pressure mat sensor M that outputs TRUE while a weight is detected on it and FALSE when no weight is detected on it.
The alarm also has a key K that turns the alarm on and off. K outputs a TRUE signal when the alarm is switched on and FALSE when the alarm is off.
The alarm output A sounds a bell. It should be TRUE if:
•        the alarm is on AND
•        either of the sensors D or M are set to the value TRUE.
(a)     In the space below, draw a logic circuit that will behave as described above for the inputs D, M and K and the output A.
 
(2)
(b)     Write a Boolean expression to represent the logic of this alarm system.
A=________________________________________________________________
(2)
(c)     In this alarm system, the alarm bell will sound only while the door is open or a weight is placed on the pressure mat. If someone who has stepped on to the mat moves off it, or an open door is closed, the alarm bell will stop ringing.
A D-type flip-flop could be incorporated into the logic circuit so that the alarm bell would continue to sound after a person closed the door or moved off the pressure mat.
Explain how this could be achieved. In your answer refer to:
•        why a D-type flip-flop would be suitable for this task
•        where the D-type flip-flop would need to be inserted into the circuit
•        what additional input the D-type flip-flop would need.
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(3)
(Total 7 marks)
Q6.
(a)     The table below lists six Boolean equations. Three of them are correct, the others are not. Shade the lozenges next to the three equations that are correct.
 
Equation	Correct? (Shade three)	
A ⋅ = 1		
A + B = 		
A + 1 = 1		
A ⋅( A + B ) = A		
A + ( A ⋅B ) = B		
A ⋅1 = 1		
(3)
(b)     Use Boolean algebra to simplify the following expression:
 
Show your working.
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Answer ___________________________
(3)
(Total 6 marks)
Q7.
(a)     Complete the truth table below for a NAND gate.
 
     NAND gate	
Input A	Input B	Output	
0	0	 	
0	1	 	
1	0	 	
1	1	 	
(1)
(b)     Multiplexors are used in electronic switching.
A 2-to-1 multiplexor has a Boolean equation where A and B are two inputs, S is the selector input, and Q is the output.
 
(i)     Complete the truth table for the above Boolean equation.
 
S	A	B			B.S	Q	
0	0	0	 	 	 	 	
0	0	1	 	 	 	 	
0	1	0	 	 	 	 	
0	1	1	 	 	 	 	
1	0	0	 	 	 	 	
1	0	1	 	 	 	 	
1	1	0	 	 	 	 	
1	1	1	 	 	 	 	
(3)
(ii)     Draw a circuit for the Boolean equation in the rectangle below.
 
(4)
(iii)     By considering its inputs and outputs, describe what the 2-to-1 multiplexor circuit does.
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(1)
(Total 9 marks)
Q8.
(a)     Complete the truth tables for the following logic gates.
OR gate
 
Input A	Input B	Output	
0	0	 	
0	1	 	
1	0	 	
1	1	 	
NAND gate
 
Input A	Input B	Output	
0	0	 	
0	1	 	
1	0	 	
1	1	 	
(2)
(b)     Represent the following Boolean equation as a logic circuit by completing the diagram below.

(5)
(c)     Simplify the following expression.
 
Show each stage of your working in the space below.
(2)

 
Final answer ________________________________________________________
(1)
(Total 10 marks)
Q9.
(a)     State the names of the logic gates represented by each of the three truth tables below.
 
Input A	Input B	Output	 	
0	0	0	 	
0	1	0	Logic gate name_______________	
1	0	0	 	
1	1	1	 	
 
Input A	Input B	Output	 	
0	0	1	 	
0	1	0	Logic gate name _______________	
1	0	0	 	
1	1	0	 	
 
Input A	Input B	Output	 	
0	0	0	 	
0	1	1	Logic gate name _______________	
1	0	1	 	
1	1	0	 	
(3)
(b)     Simplify the following Boolean expressions.
(i)      B . (A+)
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(ii)     A . B + B
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(iii)     
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(2)
(c)     Draw a logic circuit for the following Boolean expression:
Q = (A ⊕ B) . B
You will need to make use of the symbols below when drawing your logic circuit.

(2)
(Total 9 marks)
Q10.
(a)     Represent the Boolean equation Q =   as a logic circuit by drawing a diagram in the space below using only the following symbols:

AND	NOT	
 
(3)
(b)     Use the following truth tables to demonstrate that A + B =  
 
A	B	A + B	 	A	B					
0	0	 	 	0	0	 	 	 	 	
0	1	 	 	0	1	 	 	 	 	
1	0	 	 	1	0	 	 	 	 	
1	1	 	 	1	1	 	 	 	 	
(4)
(c)     What is the name commonly associated with the statement A + B =   ?
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(1)
(d)     Simplify the Boolean expression below.
A.B. + A. 
Show each stage of your working in the space below.

 
(2)
Final answer ________________________________________________________
(1)
(Total 11 marks)
Q11.
(a)     Complete the truth tables for the following logic gates.
 
AND Gate	 	XOR Gate	
Input X	Input Y	Input Q	 	Output X	Input Y	Output Q	
0	0	 	 	0	0	 	
0	1	 	 	0	1	 	
1	0	 	 	1	0	 	
1	1	 	 	1	1	 	
(2)
(b)     A line-following robot has three sensors. It moves along a black line on a white background whilst the following conditions are met:
•        the ultrasonic sensor U does not detect any obstacle
•        either, but not both, of the infrared sensors L and R are on the black line.
Sensor U returns 1 if it detects an obstacle and 0 if the path is clear.
Sensors L and R each return 1 if they detect black and 0 if they detect white.
A logic circuit will process the input from the sensors and produce an output M.
M should be 1 if the robot is to move and 0 if the robot should stop.
(i)      Represent the output M as a Boolean expression.
M = ________________________________________________________
(3)
(ii)     The following symbols are used to represent logic gates:

      NOT                          OR                            AND	

      XOR                        NOR                        NAND 	
Using a combination of any of the above logic gates draw a logic circuit for this system in the box below. You will not need to use all of the different types of logic gates.
 
(3)
(c)     Apply De Morgan’s Law(s) to the following expression and simplify the result.
 
Show the stages of your working.
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(2)
Final answer ________________________________________________________
(1)
(Total 11 marks)
Q12.
The diagram below shows a logic circuit.
 
(a)     Write a Boolean expression for D.
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(1)
(b)     Write a Boolean expression for B.
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(1)
(c)     The diagram below shows a different logic circuit.
 
(i)      Complete the truth table below for the logic circuit in the diagram above.
 
Inputs	Outputs	
X	Y	C	S	
0	0	 	 	
0	1	 	 	
1	0	 	 	
1	1	 	 	
(2)
(ii)     What arithmetic function does the logic circuit in the diagram above perform?
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(1)
(d)     Without using a truth table, simplify the Boolean expression below.
( X + Y ) . ( X +  )
Show the stages of your working.
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(3)
Final answer ________________________________________________________ 
(1)
(Total 9 marks)
Q13.
(a)     Complete the truth tables for the following logic gates.
 
NAND Gate	
Input
X	Input
Y	Output
Q	
0	0	 	
0	1	 	
1	0	 	
1	1	 	
 
NOR Gate	
Input
X	Input
Y	Output
Q	
0	0	 	
0	1	 	
1	0	 	
1	1	 	
(2)
(b)     Represent the Boolean equation Z =  .  + C in the form of a logic circuit by drawing a diagram in the space below using the following symbols.
	
OR	AND	NOT	
 
(3)
(c)     Simplify the Boolean expression below.
 
Show each stage of your working.
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(3)
Final answer ________________________________________________________
(1)
(Total 9 marks)
Q14.
The diagram below shows a logic circuit.
 
Complete the truth table for the inputs that have been given.
 
Inputs	 	 	 	
A	B	C	D	E	F	G	H	K	
0	0	1	1	0	0	 	 	 	
0	1	1	1	0	1	 	 	 	
1	0	1	1	1	0	 	 	 	
1	1	1	1	1	1	 	 	 	
(Total 3 marks)
Q15.
Write the following Boolean expressions in their simplest forms.
(a)	 	
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(b)	 	
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(c)	 	
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(1)
(d)    A . (B+1)
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(1)
(Total 4 marks)
Q16.
(a)     Complete the truth tables for the following logic gates.
 
OR Gate	 	XOR Gate	
Input A	Input B	Output Q	 	Input A	Input B	Output Q	
0	0	 	 	0	0	 	
0	1	 	 	0	1	 	
1	0	 	 	1	0	 	
1	1	 	 	1	1	 	
(2)
(b)     Represent the Boolean equation Q = A + B·. as a logic circuit by drawing a diagram of it in the space below.
 
(3)
(c)     Simplify the Boolean expression:
B·(A + )
Show your working.
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(3)
(Total 8 marks)
Q17.
Simplify the Boolean expression:
 
Show your working.
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(Total 3 marks)
Q18.
The figure below shows a logic circuit.
  
(a)     Complete the truth table below for the logic circuit shown in the above figure. Write the correct value of the output Q for each of the listed sets of inputs.
 
Input 
A	Input 
B	Input 
C	Output 
Q	
1	0	1	 	
0	1	0	 	
0	1	1	 	
(3)
(b)     Two of the gates in the circuit shown in the above figure could be replaced by a single gate.
(i)      Which two gates could be replaced?
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(1)
(ii)     What single gate would be used instead?
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(1)
(c)     Why is it an advantage to use as few gates as possible in a logic circuit?
(1)
(Total 6 marks)
Q19.
(a)     Look at the truth table below.
 
Input A	Input B	Output Q	
0	0	1	
0	1	0	
1	0	0	
1	1	0	
What logic gate does the table represent?
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(1)
(b)     An interior light in a two-door car is controlled by two switches that the driver can turn on or off and two sensors, one per door.
The switches are named A and B.
The door sensors are named C and D. 
The interior light is named L.
If a door is open the output of its sensor is on.
If a door is closed the output of its sensor is off.
•        If both switches A and B are off then the light L is always off.
•        If switch A is on the light L is always on.
•        If switch B is on and switch A is off then:
○        the light L turns on if one or more of the car doors is opened
○        the light L turns off if both of the doors are closed.
The following symbols are used to represent logic gates:
	
AND	OR	NOT	
(i)      Using only AND, OR and NOT gates draw a logic circuit for this system in the box below. You may not need to use all three types of gate.
 
(3)
(ii)     Write a Boolean expression to represent the logic of the interior light system.
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(1)
(c)     Simplify the Boolean expression below, showing your working.
  
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(3)
(Total 8 marks)
Q20.
(a)     Complete the truth tables for the following logic gates.
         OR gate                                                                     AND gate
 
Input
A	Input 
B	Output	 	Input
A	Input 
B	Output	
0	0	 	 	0	0	 	
0	1	 	 	0	1	 	
1	0	 	 	1	0	 	
1	1	 	 	1	1	 	
(2)
(b)     (i)     A single output Q is produced from three inputs A, B and C. Output Q is required to be 1 only if inputs A and B are 1, or input C is 1 and input B is 0.
Express this as a Boolean equation.
Q = _____________________________________________________
(2)
(ii)     Represent this Boolean equation diagrammatically by completing the logic gate diagram below.
 
(4)
(Total 8 marks)
Q21.
What would be the result of performing each of the following logical operations?
(a)     NOT 01001111
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(b)     00110000 OR 00000010
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(c)     11000001 AND 00010011
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(d)     00000101 XOR 10001110
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(1)
(Total 4 marks)
Q22.
The diagram below shows two masking operations.
 
(a)     Give the content of Result 1 when Mask 1 is applied to Test using the AND operation.
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(1)
(b)     What logical operation must be used to produce Result 2 when Mask 2 is applied to Set?
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(1)
(Total 2 marks)

Mark schemes
Q1.
(a)     (i)      00000010
AND
1 for mask. 1 for AND
2
(ii)     10000000
OR
1 for mask. 1 for OR
2
(b)     Repeat
     Test active
     If active = true then
       Test external motion sensor
       If external motion sensor = true then
            security light: = on
       else
            security light: = off
       endif
       Test internal motion sensor
       Test window contact
       Test door contact
       If ((internal motion sensor = true)or (window contact = false)or
       (door contact = false)) then
            Alarm: =on
       else
       Alarm off
       endif
     endif
until set = false
1 mark for suitable loop including termination.
1 mark for testing set.
1 mark for If correctly used with endif.
1 mark for testing external sensor and handling light.
1 mark for testing all three sensors (and alarm on.)
2 marks for a single if construct, just 1 if there are 3 separate ifs
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[11]
Q2.
(a)     Mark is for AO1 (knowledge)
XOR // EOR // Exclusive OR;
1
(b)     Mark is for AO2 (apply)

1
(c)     Mark is for AO2 (apply)
C;
1
(d)     Marks are for AO2 (apply)
 
C	B	A	T	S	R	
0	0	0	0	0	0	
0	0	1	0	0	1	
0	1	0	0	1	1	
0	1	1	0	1	0	
Mark as follows:
1 mark: column T correct;
1 mark: column S correct;
1 mark: column R correct;
3
(e)     Mark is for AO2 (analyse)
Use this circuit on the binary number to be subtracted and add the result to the other binary number;
A. Any equivalent answers
R. Number to be added IS negative
1
(f)     3 marks for AO1 (knowledge) and 3 marks for AO1 (understanding)
1 mark for AO1 (knowledge): (increase the) data bus width;
1 mark for AO1 (understanding): enables more bits (A. data) to be transferred between main memory and the processor at one time (so fewer read/write operations needed);
1 mark for AO1 (knowledge): (increase the) clock speed;
1 mark for AO1 (understanding): enables more instructions to be executed per unit of time/second (A. calculations/operations/commands instead of instructions) // each individual instruction could be executed sooner / more quickly (A. calculation/operation/command instead of instruction);
1 mark for AO1 (knowledge): (increase the) amount of cache memory;
1 mark for AO1 (understanding): cache memory is faster than main memory so the more that can be stored in cache memory the less frequently the main memory needs to be accessed;
1 mark for AO1 (knowledge): (increase the) word length;
1 mark for AO1 (understanding): larger word size means that the processor can process more bits in one go;
1 mark for AO1 (knowledge): (change the) type of cache memory;
1 mark for AO1 (understanding): some types of cache memory can be accessed faster;
A. using memory with a faster access speed
1 mark for AO1 (knowledge): (increase the) number of general purpose registers;
1 mark for AO1 (understanding): more intermediate results/variables can be kept in processor registers rather than in main memory;
1 mark for AO1 (knowledge): (increase the) address bus width;
1 mark for AO1 (understanding): enables the processor to access a larger number of main memory locations (meaning it will not need to make as much use of virtual memory this will mean that system performance is improved);
A. allows more main memory to be installed
R. How improves mark if it is not relevant for the factor stated.
NE How improves of "program will execute faster"
Note: Marks for the factor can be awarded in either the "factor" or "how improves" part of an answer
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[13]
Q3.
(a)     (i)      AND (gate);
1
(ii)     NOR (gate);
1
(b)     (i)      
1 mark - NOT gate on input B (before any other gate);
1 mark - AND gate with inputs from A and NOT B with output connected to J;
A. 1 mark - for circuit with just AND gate with inputs from A and B connected to J
2
(ii)     
1 mark - 
1 mark - 
1 mark for combining two previous with an OR/+ and at least one of LHS and RHS are correct;
I. K= (or other letter)
I. brackets if they will not affect expression evaluation
3
(c)      
 – use of De Morgan's (twice)
 – factorising
 – from use of 1+X=1
 – final answer (from use of De Morgan’s)
Alternative answer:

 – use of De Morgan's
 – expansion of bracket
 – from use of B.B=B
 – factorising
 – final answer (from use of 1+C=1)
Mark as follows
The above examples show two methods of simplifying and identify the identities used – there are other ways of simplifying the expression
3 marks should be awarded if the final answer is correct and there is evidence of good sound working.
2 marks should be awarded if the final answer is wrong/not achieved but evidence of good sound working.
2 marks should be awarded if the final answer is correct with some good working but the working also has incorrect use of identities
1 mark should be awarded if there is evidence of one correct use of an identity or simplification process
1 mark should be awarded if correct final answer on its own or with incorrect working
3
[10]
Q4.
(a)     Marks are for AO1 (knowledge)
 
A	B	Q		
0	0	0		
0	1	0		
1	0	0		
1	1	1		
1 mark: Table completed correctly;
1 mark: AND gate symbol drawn;
2
(b)     Marks are for AO2 (apply)
A.B.(A + B)
A.B.A + A.B.B ; [expansion of brackets]
B.A + A.B ;        [use of A.A = A]
A.B ;                  [use of A + A = A]
1 mark: Final answer: A.B;
Max 2 for working
3
(c)     (Marks are for AO2 (apply)
X + Y).(X + NOT Y)
XX + X(NOT Y) + XY + Y(NOT Y) ; [expansion of brackets]
X + X(NOT Y) + XY ; [use of X.X = X or use of Y(NOT Y) = 0 ]
X ( 1 + NOT Y + Y ) ; [use of 1 + X = 1]
1 mark: Final answer - X;
Max 2 for working
3
[8]
Q5.
(a)     All marks AO2 (apply)
 
1 mark: inputs D and M connected to an OR gate;
1 mark: inputs K and output of OR gate connected to AND gate plus output connected to A;
A a logically equivalent circuit
2
(b)     All marks AO2 (apply)
A = (D + M) · K
1 mark: D + M somewhere in expression, even if full expression incorrect
1 mark: fully correct expression
A A logically equivalent expression
2
(c)     1 mark for AO1 (understanding), 1 mark for AO2 (application) and 1 mark for AO1 (knowledge)
AO1 (understanding):1 mark: Flip-flop will store the state of its input / / Flip-flop acts as memory;
AO2 (application):1 mark: Insert into circuit between the output of the OR gate and the AND gate / / after the AND gate;
AO1 (knowledge):1 mark: Clock signal / / trigger / / signal to indicate when the value (of the input) should be stored / read;
3
[7]
Q6.
(a)      All marks AO1 (understanding)
 
Equation	Correct?
(Shade three)	
A ·  = 1	 	
A + B = 		
A + 1 = 1		
A · (A + B) = A		
A + (A · B) = B	 	
A · 1 = 1	 	
If more than three lozenges shaded then take the number of incorrect answers from the number of correct answers to arrive at the total mark
3
(b)     All marks AO2 (apply)
Example solution:
 
= A · B + B· 
= B·( + )
= B · 1
= B
In any attempted solution award:
1 mark for an application of DeMorgan's law
1 mark for an application of a Boolean identity or expanding the brackets
1 mark for correct answer
A alternative methods of solution but must use Boolean algebra not truth table
3
[6]
Q7.
(a)     
Input A	Input B	Output	
0	0	1	
0	1	1	
1	0	1	
1	1	0	
One mark for having correct values in Output column;
1
(b)     (i)      
S	A	B		A.	B.S	Q	
0	0	0	1	0	0	0	
0	0	1	1	0	0	0	
0	1	0	1	1	0	1	
0	1	1	1	1	0	1	
1	0	0	0	0	0	0	
1	0	1	0	0	1	1	
1	1	0	0	0	0	0	
1	1	1	0	0	1	1	
Marking:
One mark for the A. column being correct;
One mark for the B.S column being correct;
The final Q column should follow through from the previous two columns as an OR statement;
3
(ii)     
 
One mark for NOT gate with input from S;
A just a circle on AND gate input from S
One mark for AND gate with input from NOT S and A; 
A if no NOT gate from S
One mark for AND gate with input from B and S;
One mark for output from AND gates going into OR gate with output connect to Q;
4
(iii)    A multiplexor selects one of several input lines / wires and forwards / duplicates the Boolean value on this one line onto a single line / wire;
If S is 1 then input B is output otherwise input A is output // if S is 0 then input A is output otherwise input B is output;
Note:
1 can be mapped to on / true / high
0 can be mapped to off / false / low
MAX 1
[9]
Q8.
(a)     OR gate
 
Input A	Input B	Output	
0	0	0	
0	1	1	
1	0	1	
1	1	1	
NAND gate
 
Input A	Input B	Output	
0	0	1	
0	1	1	
1	0	1	
1	1	0	
1 mark for correct output OR gate;
1 mark for correct output NAND gate;
2
(b)    
 
1 mark for inputs A and B connected to AND gate;
1 mark for inputs B and C connected to AND gate;
1 mark for output of AND (A,B input) as only connection going to NOT gate;
1 mark for output of NOT gate plus the AND gate (B,C input) going to OR gate;
1 mark OR gate as only connection going to NOT gate and output only connection to Q;
5
(c)     MAX 2 if working out is not logically sound
Example 1:

Having applied De Morgan’s correctly;

Having factorised;
Final answer: B ;
Example 2:

Having applied De Morgan’s correctly;
 
Expanded bracket;
 
Simplified elements
 
Having used C + C.D = C to simplify
 
Having used C + C.D = C to simplify again
Final answer: B ;
Truth Table Answer
 
A	B				
0	0	0	0	0	
0	1	0	1	1	
1	0	0	0	0	
1	1	1	0	1	
 	 	X	Y	Z	
1 mark for both columns marked X and Y above; (column X could be labelled A.B )
1 mark for final column Z;
1 mark for final answer: B;
3
[10]
Q9.
(a)     AND;
NOR;
XOR; A EXOR // EOR // NEQ // exclusive OR;
3
(b)     (i)      B
1
(ii)     B
1
(iii)    0;;
Award 1 mark if De Morgan's has been applied once correctly but candidate does not end up simplifying to 0
Example: 
Example:   
2
(c)     
 
Inputs A and B connected to an XOR gate;
Input from B and output of XOR gate connected to an AND gate with output going to Q;
2
[9]
Q10.
(a)    
 
1 mark – logic of first part satisfies NOT A, NOT B;
1 mark – inputs into an AND gate;
1 mark – output from AND gate passes through a NOT gate and connected to Q;
3
(b)     
A	B	A + B	
0	0	0	
0	1	1	
1	0	1	
1	1	1	
1 mark for correct A + B column;
 
A	B	 	 			
0	0	1	1	1	0	
0	1	1	0	0	1	
1	0	0	1	0	1	
1	1	0	0	0	1	
1 mark for columns  and  column being correct;
1 mark for  column being correct;
1 mark for  column being correct;
Note: Can follow through into  column from previous two
4
(c)     De Morgan's (law);
1
(d)     Mark allocation:
One mark for taking either A, NOT C or A AND NOT C 
outside of brackets to produce a correct expression;
One mark for eliminating B in a valid way;
One mark for correct final answer;
Example One:
A.B. + A. 
A (B. + ) - taking A outside of brackets;
A ((B + 1))    ( B + 1 ) = 1
Simplifying to remove B using B + 1 = 1 ;
B. +  = 
Simplifying to remove B using B. +  = ;
A A( (B + 1))→ A.;
Final answer A. 
Example Two:
A.B. + A. 
A.(B + 1) – taking outside of brackets;
(B + 1 ) = 1; - simplifying to remove B
A  A.(B + 1)→ A. 
Final answer A. 
Truth Table Method
 
A	B	C	 	A.	A.B.+ A. 	
0	0	0	 	0	0	
0	0	1	 	0	0	
0	1	0	 	0	0	
0	1	1	 	0	0	
1	0	0	 	1	1	
1	0	1	 	0	0	
1	1	0	 	1	1	
1	1	1	 	0	0	
(student answer may have more columns than this)
A mark for having correct column for A.B. + A.;
A mark for having correct column for A.;
Final answer A. 
3
[11]
Q11.
(a)     
AND Gate	
Input X	Input X	Output Q	
0	0	0	
0	1	0	
1	0	0	
1	1	1	
 
XOR Gate	
Input X	Input X	Output Q	
0	0	0	
0	1	1	
1	0	1	
1	1	0	
1 mark for each of the output columns
2
(b)	(i)		
[Brackets are not necessary]
1 mark for use of correct operands (L,R,U);
1 mark for use of XOR with L,R;
1 mark for NOT U anded with other part;
 
alternative:		
1 mark for use of correct operands (L,R,U);
1 mark for alternative XOR expression;
1 mark for AND NOT U;
 
alternative:		
1 mark for use of correct operands (L,R,U);
1 mark for alternative XOR expression;
1 mark for AND NOT U;
Acceptable notation for symbols
~ for NOT
X.Y allow X AND Y, XэY,X)Y, XY
X+Y allow X OR Y, X(Y, X*Y
3
(ii)     
 
L, R connected to XOR gate;
U connected to NOT gate;
Output of a two input AND gate connected to M;
Max 2 if circuit does not reflect the correct logic
Alternative :
 
U connected to NOT gate;
Correct gates used for L and R before last AND gate; 
Output of a two input AND gate connected to M;
Alternative :
 
Marked as above alternative.
3
(c)     Solution 1:
	
[Application of De Morgan’s Law –1 mark]
[allow simplification of double nots at same time]
[Simplification of A.A to A –1 mark]
[Correct solution – 1 mark]	
Solution 2:
	
[Application of De Morgan’s Law –1 mark]

[allow simplification of double nots at same time]

[Simplification of NOT A OR NOT A to NOT A – 1 mark]

[De Morgan’s again to correct solution – 1 mark]	
1 mark for De Morgan;
1 mark for simplification;
1 mark for final answer;
Other notations as for section (b)
No working marks for truth table solution (asked to use De Morgan’s in question)
3
[11]
Q12.
(a)     X  Y;
 
A alternative notations:
X XOR Y 
X EOR Y
X AND NOT Y OR NOT X AND Y
Acceptable notation for symbols :
For X.Y allow X∧Y, X∩Y, XY 
For X+Y allow XvY,XUY 
For X allow ~X
1
(b)     ; 
A alternative notations : X AND NOT Y;
1
(c)     (i)
Inputs	Outputs	
X	Y	C	S	
0	0	0	0	
0	1	0	1	
1	0	0	1	
1	1	1	0	
One mark for C column;
One mark for S column;
2
(ii)     Addition // adder;
A sum;
1
(d)     
 	[Fully expanding brackets – 1 mark]	
	[Recognising X.X = X OR Y. = 0 –1 mark]	
	[Taking X outside brackets – 1 mark]	
	X[Final Answer, 1 mark]	
Alternative Answer : (Distributive)
	[Use of distributive law – 1 mark]	
	[Recognising Y .  = 0 – 1 mark]	
X + 0 = X 	[ 1 mark ]	
X 	[Final Answer, 1 mark]	
Alternative Answer : (De Morgan’s)
	[Use of De Morgan’s – 1 mark]	
 
	[Two further applications of De Morgan’s]	
 
	[Taking X outside brackets – 1 mark]
[Recognising ~Y + Y = 1 – 1 mark]	
	[Recognising X.1=X – 1 mark]	
 
X=Q	[Final answer, 1 mark]	
Max 3 for working/method;
1 for final answer
X on own with no working gains 1 mark.
Max 4
[9]
Q13.
(a)     
NAND	NOR	
1	1	
1	0	
1	0	
0;	0;	
2
(b)     
 
1 mark for NOT gates on both A and B;
1 mark for AND with inputs from  and ; 
A inputs from A and B
1 mark for OR gate with inputs from AND gate output and C and output connected to Z;
3
(c)      
; ; 2 marks – 1 each for De Morgans rule for each side of the central OR (award the mark for right hand expression, even if double NOT over B is not cancelled)
 Recognising NOT A OR NOT A is NOT A, and producing a correct expression
+1; Recognising B or NOT B is 1
Final answer 1 ;
Alternative answer
; Application of De Morgan’s to entire expression
; Cancellation of NOTs; 1 mark – De Morgans on entire expression
 Recognising A and A is A
 Recognising B ANDed with its complement is 0
 Recognising 0 AND anything is 0
Final answer 1 ;
Note: Marks can be awarded for the skills above if seen but Max 3 (out of 4) for whole question if working has errors in it
A T, True for 1 and F, False for 0
A alternative notations :
•        For X.Y allow X AND Y, X ∧ Y,X∩Y, XY
•        For X+Y allow X OR Y, X v Y, X U Y
•        For  allow NOT X, ¬X
Or by truth table M = marking point
 
Max 3 for stages, 1 for final answer
4
[9]
Q14.
G	H	K	
0	1	1	
1	1	0	
1	0	1	
1	0	1	
;	;	;	
1 mark for each correct column
[3]
Q15.
 becomes A + B ;
A (A+B);
A A OR B;
B+ B. becomes B ;
A B+ A.  becomes A ;
A (B+1) becomes A ;
1 mark for each
[4]
Q16.
(a)    
 
1 mark for each correct output column
A True for 1, False for 0
2
(b)     
 
1 mark for NOT gate correctly linked to input C;
1 mark for AND gate correctly linked to B and  as input; 
A if AND gate linked directly to C
1 mark for OR gate with inputs from A and the output of an AND gate and output connected to Q;
3
(c)     Algebraic solution:
B.( A +  )
B.A + B.          [1 mark for expansion of brackets ]
B.A + 0              [1 mark for identifying that B. = 0 ]
B.A                    [1 mark for correct answer]
Truth table solution:
 
1 mark for both columns X and Y correct
1 mark for column Z correct
1 mark for correct answer (B.A)
Any other method:
If student has used any other method to arrive at correct answer then award marks as follows:
1 mark for correct answer, no working out
2 marks for correct answer with working out, not all steps shown.
3 marks for correct answer with all steps of working out shown.
A True for 1, False for 0
A alternative notations :
•        For X.Y allow X AND Y, X∧Y ,X∩Y, XY
•        For X+Y allow X OR Y, X∨Y , XUY
•        For  allow NOT X, ¬X
3
[8]
Q17.
Algebraic Solution:
 
Method 1	Method 2	
     + A 

     =  +  + A 

    = 1 +  

     = 1	     + A 

     =  

    =  

     = 
      = 1	
1 mark for an application of a DeMorgan’s law
1 mark for realisation that A +  +  = 1 +  or  =  (must be written in method, not just inferred that student has done this if arrives at correct answer)
1 mark for correct answer
Truth table solution:
 
1 mark for column Y correct
1 mark for column Z correct
1 mark for correct answer
Any other method:
If student has used any other method to arrive at correct answer then award marks as follows:
1 mark for correct answer, no working out
2 marks for correct answer with working out, not all steps shown.
3 marks for correct answer with all steps of working out shown.
A True for 1, False for 0
A alternative notations :
•        For X.Y allow X AND Y, X∧Y ,X∩Y, XY
•        For X+Y allow X OR Y, X∨Y , X∪Y
•        For  allow NOT X, ¬X
[3]
Q18.
(a)     1; A True
1; A True
0; A False
3
(b)     (i)      AND and NOT
1
(ii)      NAND // NAND gate
R NOT AND
1
(c)     Minimise cost of production;
Reduce propagation delay//speed up processing;
Minimise heat generated;
Reduce power consumption;
NE simpler to produce/makes circuit simpler
NE reduce number of gates in chip
1
[6]
Q19.
(a)     NOR (Gate) 
I case of answer i.e. nor is allowed
1
(b)     (i)     Solution 1:
 
Solution 2:
 
Solution 3 (solution 1 plus check for A off):
 
Solution 4 (solution 2 plus check for A off):
 
1 mark for each correctly linked gate that is marked with a #

A 3-input OR gate 
P1 for any unnecessary gates in a solution that would otherwise get 3 marks.
P1 for any solution that would not correctly implement the logic but would otherwise get 3 marks. 

Mark from left to right until first mistake encountered then from right to left. When marking left to right award 1 mark for each gate correctly connected to its inputs. When marking right to left award 1 mark for each gate correctly connected to its output.
3
(ii)     A + B.(C+ D)
A + B.C+ B.D
A + .B. (C+ D)
A + .B.C+ .B.D

A Insertion of extra brackets that do not affect logic of expression
Note: Expression does not need to match diagram drawn in (i).
A alternative notations :
•        For X.Y allow X AND Y, X ∧ Y , X ∩ Y, XY
•        For X+Y allow X OR Y, X ∨ Y , X ∪ Y
•        For  allow NOT X, ¬X
1
(c)     Algebraic Solution:
 + B.              [Application of DeMorgan’s Law 1 mark]
A.B + B.                  [Common term B taken out 1 mark]
B.(A + ) // B.1
B                                [Correct answer 1 mark]
A alternative notations :
•        For X.Y allow X AND Y, X ∧Y , X ∩ Y, XY
•        For X+Y allow X OR Y, X∨ Y , X∪Y
•        For X allow NOT X, ¬X
Truth Table Solution:
 
1 mark for both columns X and Y correct
1 mark for column Z correct
1 mark for correct answer (B)

A Rightmost column labelled as L or Q
3
[8]
Q20.
(a)                                      OR                                                                                   AND
Input A	Input B	Output	 	Input A	Input B	Output	
0	0	0	 	0	0	0	
0	1	1	 	0	1	0	
1	0	1	 	1	0	0	
1	1	1	 	1	1	1	
1 mark per correct table
2
(b)     (i)      Q = A.B + C. 
1 mark for A.B or for C.
2 marks for A.B + C.

A AND instead of .     
A OR instead of +
2
(ii)     1 mark for each gate with correct inputs;;;;
Allow two lines from B
 
4
[8]
Q21.
(i)      10110000
1
(ii)          00110010
1
(iii)        00000001
1
(iv)     10001011
1
[4]
Q22.
(a)     00001000
1
(b)     Or / XOr
1
[2]